arch.x86.isr.mgr¶
Interrupt Service Routine registration, dispatch, and IDT gate management.
Overview¶
This unit is the central ISR management layer. It maintains a two-dimensional hook table indexed by interrupt vector number and hook slot, installs naked assembly stubs (ISR_0 through ISR_255) in the IDT for all 256 vectors, and dispatches registered callbacks when interrupts fire. It also handles End-of-Interrupt (EOI) signalling to both the 8259 PIC and, when present, the Local APIC.
Each ISR stub is declared with the Free Pascal interrupt directive, which causes the compiler to generate PUSHAD/POPAD prologue and epilogue code and use IRETD to return. The stub saves EBP into the global IntReg pointer before calling the common dispatch function ISR_N.
Dependencies¶
arch.x86.israrch.x86.idtarch.x86.isr.typescore.utilarch.x86.utilio.syslog(implementation)arch.x86.isr.ioapic(implementation)
Constants¶
MAX_HOOKS is imported from arch.x86.isr.types and defines the maximum number of callbacks per vector.
Types¶
TISRHook¶
Type of a no-argument, no-return ISR callback procedure.
TISRNHookArray¶
Array of hook callbacks for a single interrupt vector.
TISRHookArray¶
Two-dimensional array of all hook callbacks, indexed by vector number then hook slot.
Functions and Procedures¶
init¶
Installs assembly ISR stubs for all 256 vectors into the IDT using arch.x86.idt.set_gate with selector $08 and ISR_RING_0 flags. All hook slots are initialised to nil during unit startup.
registerISR¶
Registers a callback for interrupt vector INT_N. Scans the hook slot array for the first empty slot (nil entry) and assigns callback to it. Up to MAX_HOOKS callbacks may be registered per vector.
INT_N— The IDT vector number (0–255).callback— The procedure to invoke when the interrupt fires.
dispatchHooks¶
Iterates through all MAX_HOOKS slots for vector INT_N and calls each non-nil callback. Does not send EOI. Used by the context switch ISR (arch.x86.proc.sched) to fire timer hooks before sending EOI independently.
Notes¶
- The internal
ISR_Nprocedure dispatches all hooks for a given vector, sends a Local APIC EOI viaarch.x86.isr.ioapic.lapic_eoi, and then sends an 8259 EOI. For slave PIC interrupts (vectors 40–47), the slave EOI ($A0) is sent before the master EOI ($20). - The context switch ISR (
arch.x86.proc.sched.context_switch_isr) replaces IDT gate 32 afterinitis called and manages its own EOI, bypassingISR_Nfor the timer vector. - The
interruptprocedure directive on each ISR stub causes Free Pascal to generate the correct PUSHAD/POPAD frame and IRETD. The EBP register at the start of this frame is saved toIntRegso that fault handlers can locate the saved register state.